There have been logic synthesis tools that automate logic synthesis for generating a netlist (a gate circuit) from a description, such as a register-transfer-level (RTL), of an integrated circuit. The logic synthesis tool generates a netlist from an input RTL so that a circuit is formed of logic gates that are optimum from viewpoints such as timing, area, and power consumption.
With the logic synthesis tool, in cases where a module defined by a user is present in an input RTL, and the module is used as an instance a plurality of times, it is typical that replacement processing of a module name is automatically performed so that the module that each instance refers to is unique. In this case, mapping to a logic gate, timing analysis, and adjustment for improvement in timing are performed after the replacement processing.
The term “module” as used herein means a definition for a logic circuit, and the term “instance” means an entity of a logic circuit itself generated from a definition. The word “unique” represents a state in which there is only one entity for one definition, and the word “nonunique” represents a state in which there are a plurality of entities for one definition.
There is known a technique in which, at the time of timing adjustment during logic synthesis, pins of a module are left as net information, so that layering of the module can be performed again after the logic synthesis, and replacing function blocks organized in a hierarchical manner makes it possible to readily modify logic after the logic synthesis. There are also known a netlist generating method for facilitating analysis with physical information taken into consideration during timing verification, and a technique for performing automatic arrangement with physical information taken into consideration.
Related art is disclosed in Japanese Laid-open Patent Publication No. 2005-122577 and Japanese Laid-open Patent Publication No. 2006-164132.
Unfortunately, conventional techniques in which, during logic synthesis, a module is made unique and a netlist is generated have the following problems.
First, making a module unique results in generation of a plurality of new modules in a netlist, and therefore the need for physical design for each module arises. In the case of a design method mainly using an automatic tool such as an application specific integrated circuit (ASIC), making a module unique hardly affects the man-hours taken for physical design. However, in the case of a design method that mainly involves operation performed by a user, such as in the case of a processor, if a module is made unique, each module generated as a result of this gives rise to the need for an operation used in physical design. This greatly affects the man-hours taken for physical design.
The timings of modules differ from one another depending on what peripheral logics are connected to the modules with which instantiation is performed in a higher layer, and depending on the timing constraints of modules for input and output interfaces. The timing violation values differ between modules with which instantiation is performed.
For example, if a “module_A” having a path 1 and a path 2 is made unique, and, as a result, a “module_A1” and a “module_A2” are obtained, there is a case where the path 1 of the “module_A1” is a target of timing adjustment, and the path 2 is not a target, whereas the path 1 of the “module_A2” is not a target of timing adjustment, and the path 2 is a target.
In this case, the “module_A” with which timing adjustment of the path 1 and timing adjustment of the path 2 are simultaneously performed does not exist. Thus, in the case of putting an optimum module as an IP macro into a library, the optimum module is not selected from modules that have been made unique.